INSTRUCCIONES PARA EL DSP **TMS320C5X**

INSTRUCCIONES DEL TMS320C5X

Mnemonic Description

ADCB Add ACCB and carry bit to ACC
ADD Add data memory value, with left shift, to ACC
ADDB Add ACCB to ACC
ADDC Add data memory value and carry bit to ACC with sign extension suppressed
ADDS Add data memory value to ACC with sign extension suppressed
ADDT Add data memory value, with left shift specified by TREG1, to ACC
APAC Add PREG, width shift specified by PM bits, to ACC
APL AND data memory value with DBMR, and store result in data memory location
BLDD Block move from data to data memory
BLDP Block move from data to program memory with destination address in BMAR
BLPD Block move from program to data memory
BSAR Barrel-shift ACC right
DMOV Move data in data memory
IN Input data from I/O port to data memory
LMMR Load data memory value to memory-papped register
LTA Load data memory value to TREG0;add PREG, with shift specified by PM bits, to ACC
LTD Load data memory value to TREG0;add PREG, with shift specified by PM bits, to ACC; and move data
LTS Load data memory value to TREG0;subtract PREG, with shift specified by PM bits, from ACC
MAC Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0;multiply data memory value by program memory value and store result in PREG
MACD Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0;multiply data memory value by program memory value and store result in PREG; and move data
MADD Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0;multiply data memory value by value specified in BMAR and store result in PREG; and move data
MADS Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0;multiply data memory value by value specified in BMAR and store result in PREG
MPYA Add PREG, with shift specified by PM bits, to ACC; multiply data memory value by TREG0 and store result in PREG
MPYS Substract PREG, with shift specified by PM bits, from ACC; multiply data memory value by TREG0 and store result in PREG
MAR Modify ARn
NOP No operation
NORM Normailize ACC
OPL OR data memory value with DBMR and store result in data memory location
OUT Output data from memory location to I/O port
POP Pop top of stack to data memory location
PSHD Push data memory value to top of stack
PUSH Push ACCL to top of stack
ROL Rotate ACC left 1 bit
ROLB Rotate ACCB and ACC left 1 bit
ROR Rotate ACC right 1 bit
RORB Rotate ACCB and ACC right 1 bit
SACH Store ACCH, with left shift, in data memory location
SACL Store ACCL, with left shift, in data memory location
SAMM Store ACCL in memory mapped register
SAR AR,{ind} Store ARn (modified in indirect addressing mode) in data memory location
SATH Barret-shift ACC right 0 to 16 bits as specified by TREG1
SATL Barrit-shift ACC right as specified by TREG1
SBB Substract ACCB from ACC
SBBB Subtract ACCB and logival inversion of carry from ACC
SFL Shift ACC left 1 bit
SFLB Shift ACCB and ACC left 1 bit
SFR Shift ACC right 1 bit
SFRB Shift ACCB and ACC right 1 bit
SMMR Store memory-mapped register in data memory location
SPAC Subtract PREG, with shift specified by PM bits from ACC
SPH Store PREG high byte, with shift specified by PM bits in data memory location
SPL Store PREG low byte, with shift specified by PM bits in data memory location
SQRA Add PREG, with shift specified by PM, to ACC: load data memory value to TREG0; square value and store result in PREG
SQRS Subtract PREG, with shift specified by PM, from ACC: load data memory value to TREG0; square value and store result in PREG
SST Store STn in data memory location
SUB Subtract data memory value, with left shift, from ACC
SUBB Subtract data memory value abd logical inversion of carry bit from ACC with sign extension suppresseded
SUBC Conditional subtract
SUBS Subtract data memory value from ACC with sign estension suppressed
SUBT Subtract data memory value, with left shift specified by TREG1, from ACC
TBLR Transfer data from program to data memory with source sddress in ACCL
TBLW Transfer data from data to program memory with destination address in ACCL
XPL Exclusive-OR data memory value with DBMR and store result in data memory location
ABS Absolute value of ACC; zero carry bit
AND AND data memory value with ACCL;zero ACCH
ANDB AND ACCB with ACC
BIT Test bit
BITT Test bit specified by TREG2
CLRC Clear status bit
CMPL 1s complement
CMPR Compare ARn with ARCR as specified by CM bits
CPL Compare data memory value with DBMR
CRGT Store ACC in ACCB if ACC > ACCB
CRLT Store ACC in ACCB if ACC > ACCB
EXAR Exchange ACC to ACCB
LACB Load ACC to ACCB
LACC Load data memory value, with left shift, to ACC
LACL Load data memory value to ACC; zero ACCH
LACT Load data memory value, with left shift specified by TREG1, to ACC
LAMM Load contents of memory-mapped register to ACCL; zero ACCH
LAR Load data memory value to ARx
LDP Load data memory value to DP bits
LPH Load data memory value to PREG high byte
LST Load data memory value to STm
LT Load data memory value to TREG0
LTP Load data memory value to TREG0; store PREG, with shift specified by PM bits, in ACC
MPY Multipli data memory by TREG0 and store result in PREG
MPYU Multiply unsigned data memory value by TREG0 and store result in PREG
NEG Negative (2a complement) ACC
OR OR data memory value with ACCL
ORB OR ACCB with ACC
PAC Load PREG, with shift specified by PM bits, to ACC
SACB Store ACC in ACCB
SAR AR, dma Store ARn direct addressed in data memory location
SETC Set status bit
SPM Set product shift mode (PM) bits
XOR Exclusive-OR data memory value ACCL
XORB Exclusive-OR ACCB with ACC
ZALR Zero ACCL and load ACCH with rouning
ZAP Zero ACC and PREG
ZPR Zero PREG
ADD #k Add short inmediate to ACC
ADD #lk, shift Add long inmediate, with left shift, to ACC
ADRK Add short inmediate to AR
AND #lk, shift AND long inmediate, with left shift, wuith ACC
APL #k AND data memory value long inmediate and store result in data memory location
B Branch unconditional
BACC Branch to program memory location specified by ACCL
BACCD Delayed branch to preogram memory location specified by ACCL
BANZ Branch to program memory location if AR not zero
BANZD Delayed branch to program memory loacation if AR not zero
BCND Branch conditional to program memory location
BCNDD Delayed branch conditional to program memory location
BD Delayed branch unconditional
CALA Call to subroutine unconditional
CALAD Delayed call to subroutine addressed by ACCL
CALL Call to subroutine unconditional
CALLD Delayed call to subroutine unconditional
CC Call to subroutine conditional
CCD Delayed call to subroutine conditional
CPL #lk Compare data memory value with long inmediate
IDLE Idle until nonmaskcable interrupt or reset
IDLE2 Idle until nonmaskcable interrupt or reset-low-power mode
INTR Software interrupt that branches program control to program memory location
LACC #lk, shift Load long inmediate with left, to ACC
LACL #k Load short inmediate to ACCL;zero ACCH
LAR #k Load short inmediate to ARx
LAR #lk Load long inmediate to ARx
LDP #k Load short inmediate to DP bits
MPY #k Multiply short inmedite by TREG0 and store result in PREG
MPY #lk Multiply long inmedite by TREG and store result in PREG
NMI Nonmaskable interrupt and globally disable interrupts (INTM=1)
OPL #lk OR data memory value with long inmediate and store result in data memory location
OR #lk, shift OR long inmediate , with left shift, with ACC
RET Return from subroutine
RETC Return from subroutine conditionally
RETCD Delayed return from subroutine conditionally
RETD Delayed return from subroutine
RETE Return from interrupt with context switch and globaly enable interrupts (INTM=0)
RETI Return from interrupt with context switch
RPT Repeat next instruction specified by data memory value
RPTB Repeat block of instriction specified by BRCR
RPTZ Clear ACC and PREG, repeat next instruction specified by long immediate
SBRK Substract short inmediate from AR
SPLK #lk Store long inmediate in data memory location
SUB #k Substract short immediate from ACC
SUB #lk, shift Substract long immediate, with left shift, from ACC
TRAP Software interrupt that branches program control to program memory location 22h
XC Execute next instruction(s) conditionally
XOR #lk, shift XOR long immediate, with left shift, with ACC
XPL EXclusive-OR data memory value with long immediate and store result in data memory location

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Mnemonic	Description
ADCB	Add ACCB and carry bit to ACC
ADD	Add data memory value, with left shift, to ACC
ADDB	Add ACCB to ACC
ADDC	Add data memory value and carry bit to ACC with sign extension suppressed
ADDS	Add data memory value to ACC with sign extension suppressed
ADDT	Add data memory value, with left shift specified by TREG1, to ACC
APAC	Add PREG, width shift specified by PM bits, to ACC
APL	AND data memory value with DBMR, and store result in data memory location
BLDD	Block move from data to data memory
BLDP	Block move from data to program memory with destination address in BMAR
BLPD	Block move from program to data memory
BSAR	Barrel-shift ACC right
DMOV	Move data in data memory
IN	Input data from I/O port to data memory
LMMR	Load data memory value to memory-papped register
LTA	Load data memory value to TREG0;add PREG, with shift specified by PM bits, to ACC
LTD	Load data memory value to TREG0;add PREG, with shift specified by PM bits, to ACC; and move data
LTS	Load data memory value to TREG0;subtract PREG, with shift specified by PM bits, from ACC
MAC	Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0;multiply data memory value by program memory value and store result in PREG
MACD	Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0;multiply data memory value by program memory value and store result in PREG; and move data
MADD	Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0;multiply data memory value by value specified in BMAR and store result in PREG; and move data
MADS	Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0;multiply data memory value by value specified in BMAR and store result in PREG
MPYA	Add PREG, with shift specified by PM bits, to ACC; multiply data memory value by TREG0 and store result in PREG
MPYS	Substract PREG, with shift specified by PM bits, from ACC; multiply data memory value by TREG0 and store result in PREG
MAR	Modify ARn
NOP	No operation
NORM	Normailize ACC
OPL	OR data memory value with DBMR and store result in data memory location
OUT	Output data from memory location to I/O port
POP	Pop top of stack to data memory location
PSHD	Push data memory value to top of stack
PUSH	Push ACCL to top of stack
ROL	Rotate ACC left 1 bit
ROLB	Rotate ACCB and ACC left 1 bit
ROR	Rotate ACC right 1 bit
RORB	Rotate ACCB and ACC right 1 bit
SACH	Store ACCH, with left shift, in data memory location
SACL	Store ACCL, with left shift, in data memory location
SAMM	Store ACCL in memory mapped register
SAR AR,{ind}	Store ARn (modified in indirect addressing mode) in data memory location
SATH	Barret-shift ACC right 0 to 16 bits as specified by TREG1
SATL	Barrit-shift ACC right as specified by TREG1
SBB	Substract ACCB from ACC
SBBB	Subtract ACCB and logival inversion of carry from ACC
SFL	Shift ACC left 1 bit
SFLB	Shift ACCB and ACC left 1 bit
SFR	Shift ACC right 1 bit
SFRB	Shift ACCB and ACC right 1 bit
SMMR	Store memory-mapped register in data memory location
SPAC	Subtract PREG, with shift specified by PM bits from ACC
SPH	Store PREG high byte, with shift specified by PM bits in data memory location
SPL	Store PREG low byte, with shift specified by PM bits in data memory location
SQRA	Add PREG, with shift specified by PM, to ACC: load data memory value to TREG0; square value and store result in PREG
SQRS	Subtract PREG, with shift specified by PM, from ACC: load data memory value to TREG0; square value and store result in PREG
SST	Store STn in data memory location
SUB	Subtract data memory value, with left shift, from ACC
SUBB	Subtract data memory value abd logical inversion of carry bit from ACC with sign extension suppresseded
SUBC	Conditional subtract
SUBS	Subtract data memory value from ACC with sign estension suppressed
SUBT	Subtract data memory value, with left shift specified by TREG1, from ACC
TBLR	Transfer data from program to data memory with source sddress in ACCL
TBLW	Transfer data from data to program memory with destination address in ACCL
XPL	Exclusive-OR data memory value with DBMR and store result in data memory location
ABS	Absolute value of ACC; zero carry bit
AND	AND data memory value with ACCL;zero ACCH
ANDB	AND ACCB with ACC
BIT	Test bit
BITT	Test bit specified by TREG2
CLRC	Clear status bit
CMPL	1s complement
CMPR	Compare ARn with ARCR as specified by CM bits
CPL	Compare data memory value with DBMR
CRGT	Store ACC in ACCB if ACC > ACCB
CRLT	Store ACC in ACCB if ACC > ACCB
EXAR	Exchange ACC to ACCB
LACB	Load ACC to ACCB
LACC	Load data memory value, with left shift, to ACC
LACL	Load data memory value to ACC; zero ACCH
LACT	Load data memory value, with left shift specified by TREG1, to ACC
LAMM	Load contents of memory-mapped register to ACCL; zero ACCH
LAR	Load data memory value to ARx
LDP	Load data memory value to DP bits
LPH	Load data memory value to PREG high byte
LST	Load data memory value to STm
LT	Load data memory value to TREG0
LTP	Load data memory value to TREG0; store PREG, with shift specified by PM bits, in ACC
MPY	Multipli data memory by TREG0 and store result in PREG
MPYU	Multiply unsigned data memory value by TREG0 and store result in PREG
NEG	Negative (2a complement) ACC
OR	OR data memory value with ACCL
ORB	OR ACCB with ACC
PAC	Load PREG, with shift specified by PM bits, to ACC
SACB	Store ACC in ACCB
SAR AR, dma	Store ARn direct addressed in data memory location
SETC	Set status bit
SPM	Set product shift mode (PM) bits
XOR	Exclusive-OR data memory value ACCL
XORB	Exclusive-OR ACCB with ACC
ZALR	Zero ACCL and load ACCH with rouning
ZAP	Zero ACC and PREG
ZPR	Zero PREG
ADD #k	Add short inmediate to ACC
ADD #lk, shift	Add long inmediate, with left shift, to ACC
ADRK	Add short inmediate to AR
AND #lk, shift	AND long inmediate, with left shift, wuith ACC
APL #k	AND data memory value long inmediate and store result in data memory location
B	Branch unconditional
BACC	Branch to program memory location specified by ACCL
BACCD	Delayed branch to preogram memory location specified by ACCL
BANZ	Branch to program memory location if AR not zero
BANZD	Delayed branch to program memory loacation if AR not zero
BCND	Branch conditional to program memory location
BCNDD	Delayed branch conditional to program memory location
BD	Delayed branch unconditional
CALA	Call to subroutine unconditional
CALAD	Delayed call to subroutine addressed by ACCL
CALL	Call to subroutine unconditional
CALLD	Delayed call to subroutine unconditional
CC	Call to subroutine conditional
CCD	Delayed call to subroutine conditional
CPL #lk	Compare data memory value with long inmediate
IDLE	Idle until nonmaskcable interrupt or reset
IDLE2	Idle until nonmaskcable interrupt or reset-low-power mode
INTR	Software interrupt that branches program control to program memory location
LACC #lk, shift	Load long inmediate with left, to ACC
LACL #k	Load short inmediate to ACCL;zero ACCH
LAR #k	Load short inmediate to ARx
LAR #lk	Load long inmediate to ARx
LDP #k	Load short inmediate to DP bits
MPY #k	Multiply short inmedite by TREG0 and store result in PREG
MPY #lk	Multiply long inmedite by TREG and store result in PREG
NMI	Nonmaskable interrupt and globally disable interrupts (INTM=1)
OPL #lk	OR data memory value with long inmediate and store result in data memory location
OR #lk, shift	OR long inmediate , with left shift, with ACC
RET	Return from subroutine
RETC	Return from subroutine conditionally
RETCD	Delayed return from subroutine conditionally
RETD	Delayed return from subroutine
RETE	Return from interrupt with context switch and globaly enable interrupts (INTM=0)
RETI	Return from interrupt with context switch
RPT	Repeat next instruction specified by data memory value
RPTB	Repeat block of instriction specified by BRCR
RPTZ	Clear ACC and PREG, repeat next instruction specified by long immediate
SBRK	Substract short inmediate from AR
SPLK #lk	Store long inmediate in data memory location
SUB #k	Substract short immediate from ACC
SUB #lk, shift	Substract long immediate, with left shift, from ACC
TRAP	Software interrupt that branches program control to program memory location 22h
XC	Execute next instruction(s) conditionally
XOR #lk, shift	XOR long immediate, with left shift, with ACC
XPL	EXclusive-OR data memory value with long immediate and store result in data memory location

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TMS320C5x DSP Starter Kit User´s GuideBaja el manual completo del Starter Kit

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